SI Verify is ideal for designs where components are placed or placed and routed. If and when the nets are not routed, estimates on interconnect length and impedance are automatically considered during simulation.

Analysis & Verification Solutions offered by CADSTAR (electrical verification)

CADSTAR’s SI Verify uses a comprehensive and easy to use simulation library with a large range of models and standard components; IBIS models can be utilized and SPICE models for passive circuits can be loaded either.

The graphical Scenario Editor provides a 'what-if' scratchpad, to do topology studies and to experiment with different design strategies. In addition, powerful parameter sweep features help to explore design limits and to optimize termination networks. Si-Verify can be used interactively in a scope mode for selected nets as well as in batch-mode for an entire PCB sign-off simulation.

• It offers a seamlessly integrated complete signal integrity simulation toolset.
• It uses Constraint Manager as design navigation cockpit to launch a simulation for selected areas of the board,
• Evaluate the electrical performance, analyze reflection and crosstalk effects and calculate the relevant interconnect timing information, perform what-ifs with regard to changes of the layer stack, different track widths, track-to-track spacing.
• Define complex stimulus information driving the simulation including digital, analog and pseudo random patterns. It is possible to view the results in time and frequency domain, results can easily be stored, archived or documented in Microsoft Office applications.
• For dense HDI boards an highly accurate via geometry extraction and analysis allows to consider the parasitic impact of vias and microvias; serial data links and differential pairs suffering jitter and ISI effects can be analyzed by doing Eye-Diagram simulations.